A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.