3D NAND flash has eliminated many cell endurance limitations of the 2D technology. Nevertheless, the complex cell architecture still shows large variations across blocks. In particular, weaker data retention and read disturb characteristics create new challenges in flash management, particularly with regard to raising system-level endurance to the levels required for enterprise storage, providing sufficient RBER margins to compensate for data retention and read disturb effects, and reducing the amount of over-provisioned space to lower overall costs. Threshold voltage shifting and wear-leveling using health binning, combined with appropriate data placement and garbage collection strategies, achieve significantly better wear leveling and enhance endurance without sacrificing performance. Large-scale flash characterization can also be leveraged to create appropriate models to better predict per-block endurance characteristics required to perform efficient wear leveling. Research shows that adopting these techniques leads to overall endurance being determined by the average endurance of all blocks, rather than that of the worst blocks. The combination of all the mentioned schemes improves endurance by up to 15x compared with the baseline, even without stronger ECC.