The 3D QLC NAND flash memory characteristics exhibit remarkable challenges in terms of latency and reliability resulting in an unassertive adoption in the enterprise storage market. We demonstrate that through an innovative controller design and novel flash management algorithms these challenges can be effectively mitigated. Emphasis is given to read voltage calibration and data placement alternatives and their critical role in achieving low error-rates and low read latency performance. We present experimental results that demonstrate the improvements from various read voltage calibration and data placement schemes and discuss the specific trade-offs in accuracy and controller complexity of such schemes. Our findings demonstrate that implementing these techniques in a QLC controller not only achieves TLC-like performance but can even outperform traditional TLC controller designs which are widespread in enterprise storage systems today.

BIBTEX

@InProceedings{Pletka:2019:DataDrivenCtlrDev:FMS,
  author =       {Roman Pletka, Nikolaos Papandreou, Radu Stoica, Haralampos Pozidis, Nikolas Ioannou, Tim Fisher Aaron Fry, Kip Ingram, Andrew Walls},
  title =        {Achieving Latency and Reliability Targets with {QLC} in Enterprise Controllers},
  booktitle =    {Flash Memory Summit 2020},
  year =         2020,
  month =        nov,
  location =     {Virtual Conference},
  url =          {http://roman.pletka.ch/publications/20201112_Session_A-11_Pletka.pdf},
  doi =          {10.13140/RG.2.2.14960.17927},
  keywords =     {Flash memory, NAND flash controllers, QLC, Read heat separation}
}