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Nikolaos Papandreou, Haralampos Pozidis, Thomas Parnell, Nikolas Ioannou, Roman Pletka, Sasa Tomic, Patrick Breen, Garry Tressler, Aaron Fry, Timothy Fisher
Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory
International Reliability Physics Symposium, April 2019

3D NAND flash memory has entered dynamically into the space of enterprise server and storage systems, offering significantly higher capacity and better endurance than the latest 2D technology node. Moreover, the advancements in vertical stacking, cell design and program/read algorithms, have also enabled TLC 3D NAND flash with enterprise-level reliability, thus achieving further increase in capacity and cost-per-bit reduction. This paper presents an in-depth analysis of the bit-error characteristics of state-of-the-art 64-layer 3D TLC NAND flash with a focus on read-voltage calibration. We provide experimental measurements of the RBER and threshold voltage distributions using typical and mixed-mode test patterns of program/erase cycling, retention and read-disturb. Moreover, we quantify the RBER components attributed to threshold voltage level overlapping and on-chip 2-step program errors. Finally, we characterize how the optimal read voltages change under different device stress and we evaluate calibration schemes with different performance and complexity trade-off.

@InProceedings{papandreou:2019:iprs,
  Author =       {Nikolaos Papandreou and Haralampos Pozidis and Thomas Parnell and Nikolas Ioannou and Roman Pletka and Sasa Tomic and Patrick Breen and Garry Tressler and Aaron Fry and Timothy Fisher},
  Title =        {Characterization and Analysis of Bit Errors in {3D} {TLC} {NAND} Flash Memory},
  booktitle =    {Proceedings of the International Reliability Physics Symposium ({IRPS} 2019)},
  year =         2019,
  month =        apr
}

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